The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2018
Filed:
Jul. 05, 2016
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventor:
Sung Jae Chung, Seoul, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11575 (2017.01); H01L 27/11524 (2017.01); H01L 27/11526 (2017.01); H01L 27/11556 (2017.01); H01L 27/11548 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11575 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11548 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01);
Abstract
A semiconductor device includes a substrate including a cell region and a peripheral region adjacent to the cell region, a cell stack structure located in the cell region, the cell stack structure including vertical memory strings, a circuit located in the peripheral region, the circuit driving the vertical memory strings, and an interlayer insulating layer formed on the substrate to cover the cell stack structure and the circuit, and including air gaps located between the cell region and the peripheral region.