The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2018
Filed:
Jul. 07, 2016
Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;
Huilong Zhu, Poughkeepsie, NY (US);
Xing Wei, Beijing, CN;
Abstract
Provided are a CMOS device having a charged punch-through stopper (PTS) layer to reduce punch-through and a method of manufacturing the same. In an embodiment, the CMOS semiconductor device includes an n-type device and a p-type device. The n-type device and the p-type device each may include: a fin structure formed on a substrate; an isolation layer formed on the substrate, wherein a portion of the fin structure above the isolation layer acts as a fin of the n-type device or the p-type device; a charged PTS layer formed on side walls of a portion of the fin structure beneath the fin; and a gate stack formed on the isolation layer and intersecting the fin. For the n-type device, the PTS layer has net negative charges, and for the p-type device, the PTS layer has net positive charges.