The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Jan. 24, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Sung-soo Kim, Seoul, KR;

Koung-min Ryu, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823456 (2013.01); H01L 21/823475 (2013.01); H01L 23/528 (2013.01); H01L 23/53209 (2013.01); H01L 29/66545 (2013.01); H01L 29/7851 (2013.01);
Abstract

An integrated circuit device includes a fin-type active area extending on a substrate in a first direction, a first gate line and a second gate line extending on the fin-type active area in parallel to each other in a second direction, which is different from the first direction, a first insulating capping layer covering an upper surface of the first gate line and extending in parallel to the first gate line, a second insulating capping layer covering an upper surface of the second gate line and extending in parallel to the second gate line, wherein a height of the first gate line and a height of the second gate line are different from each other.


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