The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Jun. 14, 2016
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Takayuki Tajima, Sagamihara, JP;

Kazuo Shimokawa, Yokohama, JP;

Tatsuya Kobayashi, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 21/304 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 23/13 (2006.01); H01L 23/14 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/3043 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 24/97 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/13 (2013.01); H01L 23/147 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/49816 (2013.01); H01L 23/562 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/14181 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73209 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/8203 (2013.01); H01L 2224/83007 (2013.01); H01L 2224/92124 (2013.01); H01L 2224/97 (2013.01); H01L 2924/3511 (2013.01);
Abstract

a method of fabricating a semiconductor device is described below. The method includes stacking a plurality of semiconductor chips on each of regions in a substrate having a plurality of first grooves extending in a first direction and a plurality of second grooves extending in a second direction intersecting the first direction, the region being defined by the first grooves and the second grooves, providing an encapsulation portion covering a side of the substrate on which the semiconductor chips are stacked, removing a surface portion of the substrate on the opposite side to the side on which the semiconductor chips are stacked to expose the first grooves and the second grooves, and cutting the encapsulation portion along the first grooves and of second grooves. The device and the method can provide higher productivity.


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