The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Dec. 01, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Yuki Yagyu, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/49 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); B29C 45/14 (2006.01); H01L 23/00 (2006.01); B29C 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/561 (2013.01); B29C 45/0046 (2013.01); B29C 45/14655 (2013.01); B29C 45/14836 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/49838 (2013.01); H01L 24/49 (2013.01); H01L 24/78 (2013.01); H01L 24/97 (2013.01);
Abstract

A compact and high-reliability semiconductor device is implemented. The bonding wires situated in the vicinity of a gate, and the bonding wires situated in the vicinity of a vent facing to the gate across the center of a semiconductor chip in a molding step have a loop shape falling inwardly of the semiconductor chip, have a weaker pulling force (tension) than those of other bonding wires, and are loosely stretched with a margin. The bonding wires situated in the vicinity of the gate in the molding step are, for example, a first wire and a fifth wire to be connected with a first electrode pad and a fifth electrode pad, respectively. Whereas, the bonding wires situated in the vicinity of the vent in the molding step are, for example, a third wire and a seventh wire to be connected with a third electrode pad and a seventh electrode pad, respectively.


Find Patent Forward Citations

Yagyu, Yuki. (2018). Method for manufacturing a semiconductor device (U.S. Patent No. 10128130). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10128130

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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