The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Sep. 13, 2017
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Mari Matsumoto, Kawasaki, JP;

Shinichi Yasuda, Setagaya, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); H01L 27/11807 (2013.01); G11C 13/0021 (2013.01); G11C 13/0064 (2013.01); H01L 2027/11838 (2013.01); H01L 2027/11875 (2013.01);
Abstract

An integrated circuit according to an embodiment includes: first and second wiring lines; a memory device including a first and second terminals connected to the first and second wiring line respectively; a first transistor including a high-k metal gate; a first circuit applying a first write voltage between the first and the second terminals, and switch the resistance of the memory device from a high-resistance state to a low-resistance state; a second circuit reading the resistance of the memory device, and comparing a read value of the resistance with a predetermined value; a third circuit lowering a threshold voltage of the first transistor when the read value of the resistance is greater than the predetermined value; a fourth circuit applying a second write voltage between the first and second terminals after the threshold voltage is lowered; and a fifth circuit raising the threshold voltage of the first transistor.


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