The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Jun. 09, 2014
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Display Technology Co., Ltd., Beijing, CN;

Inventors:

Ming Zhang, Beijing, CN;

Huaxing Zu, Beijing, CN;

Yinzhong Zhang, Beijing, CN;

Zhaohui Hao, Beijing, CN;

Xiongxuan Yin, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); H01L 27/12 (2006.01); G02F 1/1345 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
G09G 3/2092 (2013.01); G02F 1/1345 (2013.01); H01L 27/124 (2013.01); G09G 2300/0426 (2013.01); H01L 27/3279 (2013.01); H01L 2224/27831 (2013.01);
Abstract

The array substrate according to the present disclosure may include within its fanout region a plurality of signal transmission lines for transmitting signals between a driver chip and a display region of the array substrate, and each signal transmission line may correspond to one data transmission channel. The array substrate may further include at least one impedance balancing line arranged corresponding to a signal transmission line in the plurality of signal transmission lines, wherein the impedance balancing line is electrically connected to the signal transmission line, so that a difference between impedances of different data transmission channels within the fanout region meets a first predetermined condition.


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