The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Jan. 23, 2015
Applicant:

Robert Bosch Gmbh, Stuttgart, DE;

Inventors:

Peter Wegner, Waiblingen, DE;

Jochen Ulrich Haenger, Neckarwestheim, DE;

Markus Schweizer, Vaihingen/Enz, DE;

Carsten Gebauer, Boeblingen, DE;

Bernd Mueller, Leonberg, DE;

Thomas Heinz, Stuttgart, DE;

Assignee:

Robert Bosch GmbH, Stuttgart, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/14 (2006.01); G06F 11/07 (2006.01); G06F 8/656 (2018.01);
U.S. Cl.
CPC ...
G06F 12/1433 (2013.01); G06F 8/656 (2018.02); G06F 11/076 (2013.01); G06F 11/0724 (2013.01); G06F 12/1441 (2013.01); G06F 2201/835 (2013.01);
Abstract

A method for the coexistence of software having different safety levels in a multicore processor which has at least two processor cores (). A memory range () is associated with each processor core () and a plurality of software (SW, SW) is processed on one of the processor cores () having a predefined safety level. The plurality of software (SW, SW) is processed having a predefined safety level only on the processor core () with which the same safety level is associated, in which during the processing of the plurality of software (SW, SW), the processor core () accesses only the protected memory range () which is permanently associated with this processor core ().


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