The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Jan. 26, 2016
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Optoelectronics Technology Co., Ltd., Beijing, CN;

Inventors:

Hongyan Xing, Beijing, CN;

Yanyan Yin, Beijing, CN;

Jing Xue, Beijing, CN;

Bin Ma, Beijing, CN;

Liang Zhao, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G02F 1/13 (2006.01); G02F 1/1345 (2006.01); G02F 1/1333 (2006.01); G06F 3/041 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136204 (2013.01); G02F 1/1309 (2013.01); G02F 1/1368 (2013.01); G02F 1/13454 (2013.01); G02F 1/136286 (2013.01); G02F 1/13338 (2013.01); G02F 2001/133302 (2013.01); G02F 2001/136254 (2013.01); G06F 3/041 (2013.01);
Abstract

The present disclosure relates to a display panel, a liquid crystal display device and a test method thereof. The display panel includes a display area and a GOA circuit area. The GOA circuit area includes a plurality of GOA units arranged on a TFT substrate and metal areas arranged at positions of a CF substrate corresponding to the GOA units, which constitute capacitor structures with the GOA units. The display panel further includes signal lines electrically connected with the capacitor structures and test points elicited through the signal lines. By means of the above configuration, the position where short circuit/open circuit occurs in the GOA circuit area can be found quickly by monitoring the voltage on the test point, thereby shortening the time of seeking ESD and short circuit/open circuit, increasing the analyzing and improving speed.


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