The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

Nov. 21, 2017
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Display Technology Co., Ltd., Beijing, CN;

Inventors:

Pijian Jia, Beijing, CN;

Zhaohui Hao, Beijing, CN;

Lin Li, Beijing, CN;

Lingqi Meng, Beijing, CN;

Huzhao Shi, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
G02F 1/134363 (2013.01); G02F 1/13439 (2013.01); G02F 1/134336 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G02F 2001/134318 (2013.01); G02F 2001/136295 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01);
Abstract

The present disclosure provides an array substrate, manufacturing method thereof and a display device. A method of manufacturing an array substrate includes: sequentially forming a common electrode line, a first insulating layer, a pixel electrode, and a second insulating layer, and forming a via that is in communication with the common electrode line. The method further comprises, after forming the via, forming a common electrode that covers the via through a patterning process, wherein the patterning process includes etching a portion of the via covered with the common electrode to form an isolated region. The isolated region includes a region at an inner side of a first edge of the via. The first edge is an edge of the via adjacent to or stacked with the pixel electrode. The via further includes a second edge that is neither adjacent to nor stacked with the pixel electrode.


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