The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2018

Filed:

May. 22, 2015
Applicant:

Cirrus Logic, Inc., Austin, TX (US);

Inventors:

Martin Joseph Gabriel, III, Austin, TX (US);

Jason Hwang, Taipei, TW;

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2014.01); G01R 31/02 (2006.01); G01R 1/073 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/26 (2013.01); G01R 1/073 (2013.01); G01R 31/02 (2013.01); G01R 31/2894 (2013.01);
Abstract

Systems and methods for multi-site placement of singulated semiconductor devices are presented. The systems and methods for multi-site placement may facilitate multi-site testing of the singulated semiconductor devices. A method may include determining a quantity of singulated semiconductor devices to be arranged in a test configuration. The method may also include determining, using a data processing device, a test configuration in response to the quantity. In further embodiments, the method may include placing the singulated semiconductor devices in a test frame according to the test configuration.


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