Signal phase tracking with high resolution, wide bandwidth and low phase noise using compound phase locked loop

Abstract

A clock recovery circuit for providing clock recovery from a burst signal that is periodically present and absent in a noisy channel. The recovery circuit includes an outer main tracking second-order phase locked loop (PLL) having an analog phase detector, a digital loop filter, and an analog/digital hybrid numerically controlled oscillator (NCO) that operates so that the clock recovery frequency is 'frozen' to its last value from the previous burst and the phase detector is disabled during the gaps between data bursts. The NCO is implemented with an inner loop PLL that operates as a high resolution synthesizer having a low internal control bandwidth that preserves VCO phase noise. The outer main loop achieves a higher control bandwidth through direct tuning of the inner loop VCO with the outer loop tuning signal.