The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2018
Filed:
Apr. 05, 2017
Applicant:
Conversant Intellectual Property Management Inc., Ottawa, CA;
Inventors:
Peter Vlasenko, Kanata, CA;
Dieter Haerle, Villach, AT;
Assignee:
Conversant Intellectual Property Management Inc., Ottawa, CA;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); H03L 7/081 (2006.01); H03L 7/10 (2006.01); H03L 7/089 (2006.01); H03L 7/095 (2006.01);
U.S. Cl.
CPC ...
H03L 7/081 (2013.01); H03L 7/0814 (2013.01); H03L 7/0818 (2013.01); H03L 7/10 (2013.01); H03L 7/0891 (2013.01); H03L 7/095 (2013.01);
Abstract
A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.