The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2018
Filed:
Feb. 16, 2016
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Junichi Nita, Tokyo, JP;
Kazutaka Suzuki, Tokyo, JP;
Takahiro Korenari, Tokyo, JP;
Yoshimasa Uchinuma, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/76895 (2013.01); H01L 21/823475 (2013.01); H01L 21/823487 (2013.01); H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H01L 27/0207 (2013.01); H01L 29/4236 (2013.01); H01L 29/7827 (2013.01); H01L 29/0865 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A semiconductor apparatus includes a first area, a first transistor being formed in two or more divided areas of the first area, and a second area, a second transistor being formed in two or more divided areas of the second area. The number of areas of the second area is greater than the number of areas of the first area, the divided areas of the first area and the second area are alternately arranged, and the gate pad of the first transistor and the gate pad of the second transistor are formed in the second area.