The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Jul. 11, 2016
Applicant:

Junyoung Ko, Cheonan-si, KR;

Inventor:

Junyoung Ko, Cheonan-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/4853 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 25/105 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/97 (2013.01); H01L 2225/1017 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

Embodiments of inventive concepts disclosed provide a method of manufacturing a semiconductor package. The method includes mounting a plurality of semiconductor chips on a substrate having a connecting member protruding from a top surface of the substrate, applying a non-conductive paste on the substrate and the semiconductor chips, forming a supporting layer coupling each of the semiconductor chips to the substrate, aligning an interposer on the non-conductive paste, forming a non-conductive layer by applying heat while pressing the interposer and the substrate against each other, and cutting the substrate, the non-conductive layer, and the interposer into separate unit packages, each of which include a semiconductor chip.


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