The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Mar. 26, 2015
Applicant:

Denso Corporation, Kariya, Aichi-pref., JP;

Inventors:

Yoshinori Tsuchiya, Kariya, JP;

Hiroyuki Tarumi, Kariya, JP;

Shinichi Hoshi, Kariya, JP;

Masaki Matsui, Kariya, JP;

Kenji Itoh, Nagakute, JP;

Tetsuo Narita, Nagakute, JP;

Tetsu Kachi, Nagakute, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/223 (2006.01); H01L 21/20 (2006.01); H01L 29/786 (2006.01); H01L 29/04 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 21/28 (2006.01); H01L 29/417 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2233 (2013.01); H01L 21/20 (2013.01); H01L 21/28264 (2013.01); H01L 29/045 (2013.01); H01L 29/1041 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/4236 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/7787 (2013.01); H01L 29/786 (2013.01); H01L 29/41766 (2013.01); H01L 29/517 (2013.01);
Abstract

A semiconductor device includes a GaN device provided with: a substrate made of a semi-insulating material or a semiconductor; a channel-forming layer including a GaN layer arranged on the substrate; a gate structure in which a gate-insulating film in contact with the GaN layer is arranged on the channel-forming layer, the gate structure having a gate electrode arranged across the gate-insulating film; and a source electrode and a drain electrode that are arranged on the channel-forming layer and on opposite sides interposing the gate structure. The donor element concentration at the interface between the gate-insulating film and the GaN layer and at the lattice position on the GaN layer side with respect to the interface is set to be less than or equal to 5.0×10cm.


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