The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Nov. 08, 2016
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Weihan Wang, Tokyo, JP;

Toshifumi Hashimoto, Yokohama Kanagawa, JP;

Noboru Shibata, Kawasaki Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 11/56 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/32 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5642 (2013.01); G06F 3/0625 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/32 (2013.01);
Abstract

A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.


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