The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Dec. 10, 2015
Applicant:

Nano-retina, Inc., Wilmington, DE (US);

Inventor:

Tuvia Liran, Qiryat Tivon, IL;

Assignee:

NANO-RETINA, INC., Wilmington, DE (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/417 (2006.01); G11C 5/14 (2006.01); H01L 27/11 (2006.01); A61N 1/36 (2006.01); A61N 1/378 (2006.01); A61F 2/14 (2006.01);
U.S. Cl.
CPC ...
G11C 11/417 (2013.01); G11C 5/143 (2013.01); H01L 27/1104 (2013.01); A61F 2/14 (2013.01); A61N 1/36046 (2013.01); A61N 1/3787 (2013.01);
Abstract

Volatile memory is described, comprising: (i) a first inverter comprising a first p-type field effect transistor (FET) connected to a first n-type FET; (ii) a second inverter comprising a second p-type FET connected to a second n-type FET; (iii) a third p-type FET; (iv) a fourth p-type FET; and (v) a floating line connecting (i) a source of the third p-type FET, and (ii) a source of the fourth p-type FET, wherein: (a) the first data line is connected to: a gate of the second p-type FET, a gate of the second n-type FET, a drain of the third p-type FET, and a gate of the fourth p-type FET, and (b) the second data line is connected to: a gate of the first p-type FET, a gate of the first n-type FET, a drain of the fourth p-type FET, and a gate of the third p-type FET.


Find Patent Forward Citations

Loading…