The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Mar. 14, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Wanfang Tsai, Palo Alto, CA (US);

Yan Li, Milpitas, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 5/06 (2006.01); G11C 16/34 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 29/00 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0688 (2013.01); G06F 5/065 (2013.01); G06F 13/1642 (2013.01); G11C 7/106 (2013.01); G11C 7/1039 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3427 (2013.01); G11C 16/3436 (2013.01); G11C 16/3454 (2013.01); G11C 29/84 (2013.01); G06F 2205/067 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/7203 (2013.01); G11C 7/1066 (2013.01);
Abstract

Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.


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