The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Aug. 15, 2017
Applicant:

Eva Automation, Inc., Redwood City, CA (US);

Inventors:

Leo Lay, Oakland, CA (US);

Adrian Harold Chadd, Santa Clara, CA (US);

Haisong Wang, Fremont, CA (US);

Shiwei Zhao, Union City, CA (US);

Li Li, San Jose, CA (US);

Gaylord Yu, San Francisco, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/00 (2006.01); G06F 3/16 (2006.01); H04R 27/00 (2006.01); H04L 7/00 (2006.01); H04L 7/033 (2006.01); H04H 60/80 (2008.01); H04L 29/06 (2006.01); H04M 1/725 (2006.01); H04N 21/233 (2011.01); H04N 21/81 (2011.01); H04N 21/43 (2011.01); H04R 3/12 (2006.01);
U.S. Cl.
CPC ...
G06F 3/165 (2013.01); H04H 60/80 (2013.01); H04L 7/0012 (2013.01); H04L 7/0016 (2013.01); H04L 7/033 (2013.01); H04L 7/0331 (2013.01); H04L 65/4069 (2013.01); H04L 65/60 (2013.01); H04L 65/608 (2013.01); H04L 65/80 (2013.01); H04M 1/72558 (2013.01); H04N 21/233 (2013.01); H04N 21/4305 (2013.01); H04N 21/8113 (2013.01); H04R 27/00 (2013.01); H04R 3/12 (2013.01); H04R 2420/07 (2013.01);
Abstract

A processor in an electronic device may coordinate an interface clock in the electronic device with a second interface clock in a second electronic device based on time-coordination information received in packets from the second electronic device. Then, the processor captures timing information associated with the interface clock provided by an interface clock circuit to increase a resolution of a system clock. Moreover, the processor may track, using the timing information, relative drift as a function of time between the system clock and the interface clock, and may determine, based on the relative drift, an estimated time offset between the interface clock and the system clock at the future time. Next, the processor modifies a future time when the electronic device is to perform the playback operation based on the estimated time offset to determine a corrected future time, and may perform the playback operation at the corrected future time.


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