The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Apr. 28, 2016
Applicant:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, CN;

Inventors:

Hui Xia, Shenzhen, CN;

Tienchun Huang, Shenzhen, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/072 (2012.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 21/77 (2017.01); H01L 27/12 (2006.01); G02F 1/1335 (2006.01); G02F 1/1343 (2006.01); G02F 1/1333 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136227 (2013.01); G02F 1/1335 (2013.01); G02F 1/1343 (2013.01); G02F 1/1368 (2013.01); G02F 1/136277 (2013.01); H01L 21/77 (2013.01); H01L 27/12 (2013.01); H01L 27/124 (2013.01); G02F 2001/133357 (2013.01);
Abstract

An array substrate and a manufacturing method thereof are disclosed. The array substrate includes: a glass substrate; a gate electrode; a first insulating layer; a semiconductor layer; a planarization layer mounted on the first insulating layer; a source electrode and a drain electrode; a pixel electrode layer mounted on the planarization layer and the drain electrode; a second insulating layer mounted on the planarization layer, the semiconductor layer, the source electrode and the drain electrode. The array substrate can prevent bubbles from forming at through holes and thereby increasing aperture ratio. The planarization layer further increases distances between the source electrode, the drain electrode and the gate electrode, which enhances antistatic ability.


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