The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2018
Filed:
Apr. 21, 2016
Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, CN;
Shimin Ge, Shenzhen, CN;
SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Shenzhen, Guangdong, CN;
Abstract
The invention provides an array substrate and a manufacturing method thereof. The array substrate comprises a substrate body, a common electrode, a light shield layer, an insulating layer, a polycrystalline silicon layer, a gate insulating layer, a gate electrode, a medium layer and a source-drain electrode. The array substrate is characterized in that the common electrode is formed on the substrate body, the light shield layer is positioned on the common electrode, the insulating layer is positioned on the light shield layer and the common electrode, and the gate electrode is connected with the common electrode through a through hole. The manufacturing method of the array substrate includes the steps: forming the patterned common electrode and the patterned light shield layer by one-time photomask and multiple etching after a transparent conducting layer and a first metal layer are formed on the substrate body, and saving one photomask; forming an electrode through hole communicated with the common electrode and the gate electrode after photomask and etching, and subsequently manufacturing the medium layer and the source-drain electrode. The whole process has seven photomasks, machining process steps of an array substrate tube are simplified, and the manufacturing cost of the array substrate is reduced.