The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2018

Filed:

Dec. 18, 2017
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Takuya Takahashi, Tokyo, JP;

Yasutaka Shimizu, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/97 (2013.01);
Abstract

A power module includes a power semiconductor device, and a chip component arranged on first and second circuit patterns that are electrically connected to the power semiconductor device, and arranged so as to bridge the first and second circuit patterns. The chip component is arranged so that first and second electrodes are respectively positioned on the first and second circuit patterns, and the first and second electrodes and the first and second circuit patterns are respectively joined with solder layers. Between a lower surface of the chip component and the first circuit pattern and between the lower surface of the chip component and the second circuit pattern, two spacers are provided in parallel with each other respectively at positions close to the first and second electrodes. The solder layers do not exist on an inner side of the two spacers in parallel with each other.


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