The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2018
Filed:
Aug. 09, 2013
Applicant:
Snaptrack Inc., San Diego, CA (US);
Inventors:
Sebastian Brunner, Graz, AT;
Stefan Leopold Hatzl, Graz, AT;
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H01L 23/498 (2006.01); H05K 3/22 (2006.01); B23K 1/00 (2006.01); B23K 1/20 (2006.01); B23K 31/02 (2006.01); H01L 21/48 (2006.01); H01L 23/492 (2006.01); H05K 1/18 (2006.01); H05K 3/24 (2006.01); H01L 23/00 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0296 (2013.01); B23K 1/0016 (2013.01); B23K 1/20 (2013.01); B23K 31/02 (2013.01); H01L 21/4846 (2013.01); H01L 23/492 (2013.01); H01L 23/498 (2013.01); H01L 23/49838 (2013.01); H01L 24/81 (2013.01); H05K 1/18 (2013.01); H05K 3/22 (2013.01); H05K 3/34 (2013.01); H01L 24/16 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/81801 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/12042 (2013.01); H05K 3/244 (2013.01); H05K 3/3436 (2013.01); H05K 2201/10674 (2013.01); H05K 2203/0361 (2013.01); H05K 2203/04 (2013.01); H05K 2203/107 (2013.01); H05K 2203/1173 (2013.01);
Abstract
A carrier plate includes a substrate and at least one conductor track. The conductor track includes a first layer, which is applied directly on the substrate, and a second layer, which is arranged on the first layer. The second layer includes a supply line region and a soldering region. Furthermore, the second layer is completely interrupted between the supply line region and the soldering region. A device can be produced with a carrier plate and an electrical component arranged on the carrier plate.