The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2018
Filed:
Sep. 21, 2017
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Jingcheng Zhuang, San Diego, CA (US);
Frederic Bossu, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01); H03L 7/197 (2006.01); H04L 7/033 (2006.01); H04L 7/00 (2006.01); H03B 1/02 (2006.01); H03L 7/23 (2006.01); H03L 7/099 (2006.01); H03L 7/093 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1976 (2013.01); H03B 1/02 (2013.01); H03L 7/093 (2013.01); H03L 7/0992 (2013.01); H03L 7/0995 (2013.01); H03L 7/23 (2013.01); H04L 7/0008 (2013.01); H04L 7/033 (2013.01);
Abstract
A clock distribution architecture is provided in which the output clock signals from a plurality of fractional-N PLLs have a known phase relationship because each fractional-N PLL is configured to commence a phase accumulation responsive to a corresponding edge of a reference clock signal.