The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2018

Filed:

Mar. 22, 2017
Applicant:

Nichia Corporation, Anan-shi, Tokushima, JP;

Inventors:

Masatsugu Ichikawa, Tokushima, JP;

Yoshiki Inoue, Anan, JP;

Yoshiyuki Aihara, Tokushima, JP;

Takehito Shimatsu, Natori, JP;

Assignee:

NICHIA CORPORATION, Anan-Shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/62 (2010.01); H01L 27/15 (2006.01); H01L 33/00 (2010.01); H01L 25/075 (2006.01); H01L 33/44 (2010.01);
U.S. Cl.
CPC ...
H01L 33/62 (2013.01); H01L 27/153 (2013.01); H01L 33/0079 (2013.01); H01L 25/0753 (2013.01); H01L 33/44 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/8192 (2013.01); H01L 2224/97 (2013.01); H01L 2933/0025 (2013.01); H01L 2933/0033 (2013.01); H01L 2933/0066 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes: providing a support with a semiconductor light-emitting element including a first electrode and a second electrode; providing a base including a first interconnect terminal and a second interconnect terminal; forming a first metal layer on the support to cover the first and the second electrodes; forming a second metal layer on the base to cover the first and the second interconnect terminals; arranging the first and second electrodes and the first and second interconnect terminals to respectively face each other, and providing electrical connection therebetween by atomic diffusion; and rendering electrically insulative or removing portions of the first metal layer and the second metal layer that are outside thereof defined between the first and second electrodes and the first and second interconnect terminals.


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