The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2018

Filed:

Aug. 29, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Francesco Carobolante, San Diego, CA (US);

Fabio Alessio Marino, San Marcos, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/93 (2006.01); H01L 23/00 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/93 (2013.01); H01L 24/08 (2013.01); H01L 29/0649 (2013.01); H01L 29/66174 (2013.01); H01L 29/66189 (2013.01); H01L 27/0808 (2013.01);
Abstract

Certain aspects of the present disclosure provide a semiconductor variable capacitor based on a buried oxide process. The semiconductor variable capacitor generally includes a first conductive pad coupled to a first non-insulative region and a second conductive pad coupled to a second non-insulative region. The second non-insulative region may be coupled to a semiconductor region. The capacitor may also include a first control region coupled to the first semiconductor region such that a capacitance between the first conductive pad and the second conductive pad is configured to be adjusted by varying a control voltage applied to the first control region. The capacitor also includes an insulator region disposed below the semiconductor region, wherein at least a portion of the first non-insulative region is separated from the second non-insulative region by the insulator region such that the first conductive pad is electrically isolated from the second conductive pad.


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