The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2018

Filed:

Jan. 17, 2017
Applicants:

Jin Taek Park, Hwaseong-si, KR;

Young Woo Park, Seoul, KR;

Jae Duk Lee, Seongnam-si, KR;

Inventors:

Jin Taek Park, Hwaseong-si, KR;

Young Woo Park, Seoul, KR;

Jae Duk Lee, Seongnam-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/792 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); G11C 16/04 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/513 (2013.01); G11C 16/0483 (2013.01); H01L 21/28273 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 29/4234 (2013.01); H01L 29/42324 (2013.01); H01L 29/4916 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7789 (2013.01); H01L 29/7926 (2013.01); H01L 29/42364 (2013.01);
Abstract

There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.


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