The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2018
Filed:
Jul. 25, 2016
Applicant:
Wafertech, Llc, Camas, WA (US);
Inventor:
Swen Wang, Camas, WA (US);
Assignee:
WAFERTECH, LLC, Camas, WA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/06 (2006.01); H01L 27/11521 (2017.01); H01L 21/28 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 21/761 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0646 (2013.01); H01L 21/28273 (2013.01); H01L 21/761 (2013.01); H01L 27/11521 (2013.01); H01L 29/41775 (2013.01); H01L 29/42324 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract
A method for forming a non-volatile memory cell is provided. The method comprises: forming a field region with a first impurity type in a semiconductor substrate, the field region having a first impurity concentration; forming a plurality of spaced apart higher concentration regions with the first impurity type within the field region, the higher concentration regions each having a higher concentration than the first impurity concentration; and forming a plurality of floating gate transistors in the field region between the higher concentration regions.