The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2018

Filed:

Feb. 03, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Shinpei Watanabe, Tokyo, JP;

Shinichi Uchida, Tokyo, JP;

Tadashi Maeda, Tokyo, JP;

Kazuo Henmi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/64 (2006.01); H01F 38/14 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/645 (2013.01); H01F 38/14 (2013.01); H01L 23/3114 (2013.01); H01L 23/4952 (2013.01); H01L 23/49513 (2013.01); H01L 23/49541 (2013.01); H01L 23/49575 (2013.01); H01L 24/05 (2013.01); H01L 24/48 (2013.01); H01L 28/10 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/48245 (2013.01);
Abstract

A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.


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