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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10115649 B1

PDFFull Text
Date of Patent:
Oct. 30, 2018

Filed:

Dec. 21, 2017

External connection mechanism, semiconductor device, and stacked package

Applicant:

Tohoku-microtec Co., Ltd, Sendai-shi, Miyagi, JP;

Inventor:

Makoto Motoyoshi, Miyagi, JP;

Assignee:

TOHOKU-MICROTEC CO., LTD., Sendai-shi, JP;

Attorney:

Metrolexis Law Group, PLLC

Primary Examiner:

George Fourson, Iii

Int. Cl.
CPC ...
H01L 23/485 (2006.01); H01L 23/31 (2006.01); H01L 21/768 (2006.01); H01L 27/06 (2006.01); H01L 21/48 (2006.01); H01L 23/522 (2006.01); H01L 21/02 (2006.01); H01L 27/02 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3128 (2013.01); H01L 21/02513 (2013.01); H01L 21/4825 (2013.01); H01L 21/7681 (2013.01); H01L 23/3178 (2013.01); H01L 23/5226 (2013.01); H01L 27/0207 (2013.01); H01L 27/0688 (2013.01); H01L 21/7685 (2013.01); H01L 24/14 (2013.01);
Abstract

A semiconductor device encompasses a connecting base including a semiconductor substrate and a surface insulating-film on the semiconductor substrate, a passivation film covering the surface insulating-film and surface electrode on the surface insulating-film, establishing a groove that exposes a central part of the surface electrode, a barrier-metal film spanning from the bottom of the groove to an upper face of the passivation film, and micro-bumps arranged on the barrier-metal film located on the passivation film.

Find Patent Forward Citations

Motoyoshi, Makoto. (2018). External connection mechanism, semiconductor device, and stacked package (U.S. Patent No. 10115649). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10115649

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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