The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2018

Filed:

Jan. 27, 2016
Applicant:

Arm Limited, Cambridge, GB;

Inventor:

Stephen Lewis Moore, Austin, TX (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/505 (2013.01); G06F 17/5077 (2013.01); G06F 2217/12 (2013.01);
Abstract

Various implementations described herein are directed to systems and methods for controlling physical placement of a circuit design. The systems and methods may extract state groups of the circuit design by deriving state groups from each logical hierarchy of the circuit design. At each level, available state points may be grouped by similarity and stored in a state groups collection alongside grouping terms. The systems and methods may generate a state bounds file that bounds locations of the state points in the circuit design. The state bounds file may be based on the extracted state groups and the grouping terms stored in the state groups collection. The systems and methods may control physical placement of the circuit design using the state bounds file.


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