The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2018

Filed:

Apr. 27, 2017
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Sean Steedman, Phoenix, AZ (US);

Kevin Kilzer, Chandler, AZ (US);

Ashish Senapati, Tempe, AZ (US);

Justin Milks, Tempe, AZ (US);

Prashanth Pulipaka, Bangalore, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 13/00 (2006.01); G06F 13/362 (2006.01); G06F 13/26 (2006.01); G06F 13/28 (2006.01); G06F 13/40 (2006.01); G06F 13/34 (2006.01);
U.S. Cl.
CPC ...
G06F 13/362 (2013.01); G06F 13/26 (2013.01); G06F 13/28 (2013.01); G06F 13/34 (2013.01); G06F 13/4068 (2013.01);
Abstract

A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.


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