The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2018

Filed:

May. 26, 2017
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Zhenxi Tu, Shenzhen, CN;

Jing Xia, Shenzhen, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/0846 (2016.01); G06F 12/0811 (2016.01); G06F 12/0831 (2016.01); G06F 12/084 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0846 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06F 12/0831 (2013.01); G06F 2212/283 (2013.01); G06F 2212/314 (2013.01);
Abstract

A cache memory system is provided. The cache memory system includes multiple upper level caches and a current level cache. Each upper level cache includes multiple cache lines. The current level cache includes an exclusive tag random access memory (Exclusive Tag RAM) and an inclusive tag random access memory (Inclusive Tag RAM). The Exclusive Tag RAM is configured to preferentially store an index address of a cache line that is in each upper level cache and whose status is unique dirty (UD). The Inclusive Tag RAM is configured to store an index address of a cache line that is in each upper level cache and whose status is unique clean (UC), shared clean (SC), or shared dirty (SD).


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