The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2018
Filed:
Dec. 10, 2015
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Martin Eckert, Moetzingen, DE;
Eckhard Kunigkeit, Stuttgart, DE;
Otto A. Torreiter, Leingelden-Echterdingen, DE;
Quintino L. Trianni, Boeblingen, DE;
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H05K 3/34 (2006.01); H01L 25/065 (2006.01); H01L 23/498 (2006.01); H05K 3/32 (2006.01); H01L 21/66 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2886 (2013.01); G01R 31/2896 (2013.01); H01L 22/14 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H05K 3/325 (2013.01); H05K 3/341 (2013.01); H01L 23/3128 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 2224/13 (2013.01); Y10T 29/49004 (2015.01); Y10T 29/4913 (2015.01); Y10T 29/49149 (2015.01);
Abstract
A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.