The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

Mar. 30, 2017
Applicant:

Dell Products, L.p., Round Rock, TX (US);

Inventors:

Kevin W. Mundt, Austin, TX (US);

Sandor Farkas, Round Rock, TX (US);

Bhyrav M. Mutnury, Round Rock, TX (US);

Yeshaswy Rajupalepu, Bryan, TX (US);

Assignee:

Dell Products, L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/12 (2006.01); H05K 7/10 (2006.01); H05K 1/18 (2006.01); H01R 12/70 (2011.01); H05K 1/11 (2006.01); H05K 3/40 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01R 12/7076 (2013.01); H05K 1/111 (2013.01); H05K 3/4007 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10704 (2013.01); H05K 2201/10734 (2013.01);
Abstract

An information handling system (IHS) has a circuit board assembly with a dual-sided interposer substrate that is inserted between a baseboard and a processor integrated circuit having a second pattern of electrical contacts. The dual interposer substrate formed of a stack of printed circuit boards (PCBs) provides communication channels between a first coupling pad on the baseboard that has a first pattern of electrical contacts and a second coupling pad on top of the dual interposer substrate that provides the second pattern of electrical contacts. The second pattern receives another type of processor integrated circuit than a type supported by the first pattern. Stacked vias formed through the stack of PCBs electrically connect respective electrical contacts of the first and second coupling pads to form a corresponding communication channel. One or more grounded vias mitigate signal integrity (SI) anomalies on the communication channels.


Find Patent Forward Citations

Mundt, Kevin. (2018). Information handling system interposer enabling specialty processor integrated circuit in standard sockets (U.S. Patent No. 10111334). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10111334

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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