The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

May. 03, 2016
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Marko Mlinar, Horjul, SI;

Tomas Geurts, Haasrode, BE;

Manuel Innocent, Wezemaal, BE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04N 3/14 (2006.01); H04N 5/335 (2011.01); H04N 5/359 (2011.01); H04N 5/372 (2011.01);
U.S. Cl.
CPC ...
H04N 5/3592 (2013.01); H04N 5/372 (2013.01);
Abstract

An image sensor may have an array of pixels that include nested sub-pixels that each have at least one respective photodiode. An inner sub-pixel of a pixel with nested sub-pixels may have a relatively lower effective light collecting area compared to an outer sub-pixel of the pixel within which the inner sub-pixel is nested. A pixel circuit for the nested sub-pixels may include an overflow capacitor and/or a coupled gate circuit used to route charges from the photodiode in the inner sub-pixel. The lower light collecting area of the photodiode in the inner sub-pixel, with optional flicker mitigation charge routing from the coupled gates structure, may reduce the size of the capacitors required to capture photodiode and photodiode overflow charge responses. Flicker mitigation charge routing using a coupled gates structure may allow an adjustable proportion of the overflow charge to be stored in one or more storage capacitors.


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