The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

Jun. 28, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Christopher Michael Graves, Sherman, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 3/037 (2006.01); H03K 3/356 (2006.01); H03K 19/003 (2006.01); H03K 19/017 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018528 (2013.01); G11C 5/147 (2013.01); H03K 3/037 (2013.01); H03K 3/356113 (2013.01); H03K 19/00361 (2013.01); H03K 19/01707 (2013.01);
Abstract

A voltage translator translates an input signal to an output signal spanning a wide range of low voltages. An input buffer receives the input signal. A level shifter provides an output control signal. A gate control circuit provides gate control signals. An output buffer provides the output signal. The level shifter includes a pair of cross coupled P-type metal oxide silicon (PMOS) transistors each in series with an N-type metal oxide silicon (NMOS) transistor. A third NMOS transistor is coupled between an upper rail and a drain of one PMOS transistor; the gate of the third NMOS transistor is controlled by a first input control signal. A fourth NMOS transistor is coupled between the upper rail and a drain of the other PMOS transistor; the gate of the fourth NMOS transistor is controlled by a second input control signal.


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