The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

Dec. 28, 2016
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Yosuke Kajiwara, Yokohama, JP;

Kentaro Ikeda, Kawasaki, JP;

Hisashi Saito, Yokohama, JP;

Masahiko Kuraguchi, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/417 (2006.01); H01L 29/778 (2006.01); H01L 23/535 (2006.01); H01L 29/423 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4175 (2013.01); H01L 23/535 (2013.01); H01L 29/42316 (2013.01); H01L 29/7786 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01);
Abstract

A semiconductor device according to an embodiment includes: a substrate having a first plane and a second plane provided on the opposite side of the first plane; a first nitride semiconductor layer provided on the first plane; source electrodes provided on the first nitride semiconductor layer; drain electrodes provided on the first nitride semiconductor layer, each of the drain electrodes provided between the source electrodes; gate electrodes provided on the first nitride semiconductor layer, each of the gate electrodes provided between each of the source electrodes and each of the drain electrodes; a first wire provided on the second plane and electrically connected to the source electrodes; a second wire electrically connected to the drain electrodes; a third wire provided on the second plane and electrically connected to the gate electrodes; and an insulating interlayer provided between the first nitride semiconductor layer and the second wire.


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