The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

May. 12, 2016
Applicant:

Delta Electronics (Shanghai) Co., Ltd, Shanghai, CN;

Inventors:

Yuechao Li, Shanghai, CN;

Weiyi Feng, Shanghai, CN;

Weiqiang Zhang, Shanghai, CN;

Hongyang Wu, Shanghai, CN;

Ziying Zhou, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49827 (2013.01); H01L 23/49822 (2013.01); H05K 1/0263 (2013.01); H05K 1/115 (2013.01); H05K 2201/0979 (2013.01); H05K 2201/09409 (2013.01);
Abstract

The present disclosure provides a via structure and a multilayer circuit board including the via structure. The via structure is provided in three or more conductor layers in the same electrical network, the conductor layers overlapping with each other vertically and including at least one current input layer and at least one current output layer; wherein the via structure includes a plurality of rows of vias, each row of vias puncture through at least one current input layer and at least one current output layer, and a part of the rows of vias puncture through all of the conductor layers, and the other part of the rows of vias puncture through a part of the conductor layers. By using the via structure in the present disclosure, the vias are subject to even temperature and thus the lifetime of the circuit board is extended.


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