The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

Aug. 12, 2016
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Thomas Kern, Aschheim, DE;

Michael Goessel, Mahlow, DE;

Karl Hofmann, Munich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/52 (2006.01); G11C 29/42 (2006.01); G11C 11/16 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/52 (2013.01); G11C 11/1677 (2013.01); G11C 29/42 (2013.01); G11C 2029/0409 (2013.01);
Abstract

A memory device includes a memory with first memory cells and second memory cells, which are different from the first memory cells. In the first memory cells there is stored a first bit sequence and in the second memory cells there is stored a second bit sequence. The memory device includes a memory controller, which is configured to check the first bit sequence with a frequency (x/T) assigned to the first memory cells. The frequency (x/T) assigned to the first memory cells depends on an item of reliability information for the first memory cells. The memory controller is configured in the case of an error state to correct an erroneous bit of the first bit sequence and to write back at least the corrected bit into the memory. The second bit sequence is checked less often than the first bit sequence on the basis of an item of reliability information for the second memory cells.


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