The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2018
Filed:
Nov. 14, 2016
Xilinx, Inc., San Jose, CA (US);
Grigor S. Gasparyan, San Jose, CA (US);
Xiao Dong, San Jose, CA (US);
Xiaojian Yang, Sunnyvale, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Partitioning a circuit design can include determining, using a processor, a target area utilization and a target cut utilization by iterating over a range of timing violations and determining, using the processor, a worst allowed timing violation based upon the target area utilization and the target cut utilization. Circuit elements of the circuit design can be assigned to partitions, using the processor, for implementation of the circuit design in a multi-die integrated circuit based upon a partition cost calculated using the target area utilization, the target cut utilization, and the worst allowed timing violation.