The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10108249 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 23, 2018

Filed:

Apr. 01, 2014
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Seiji Seki, Tokyo, JP;

Masanori Hayashikoshi, Kanagawa, JP;

Kiyoshi Nakakimura, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 3/06 (2006.01); G06F 12/06 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3275 (2013.01); G06F 1/3225 (2013.01); G06F 1/3206 (2013.01); G06F 1/3234 (2013.01); G06F 3/0634 (2013.01); G06F 12/0646 (2013.01); G06F 13/1694 (2013.01); G06F 2212/1028 (2013.01); Y02D 10/13 (2018.01); Y02D 10/14 (2018.01); Y02D 50/20 (2018.01);
Abstract

The memory power consumption is reduced more than in the past by performing a power control suitably for a nonvolatile memory. A memory control circuit is provided with a first register group for a CPU to perform separately initial setting of the operation mode (power OFF, standby, and power ON) of plural banks included in a nonvolatile memory, for every task of a program executed by the CPU, and an access determination unit which determines a bank to which an access from the CPU takes place, on the basis of the access address for instruction fetching and the kind of the fetched instruction. The memory control circuit switches the operation mode of each of the banks on the basis of the setting value of the first register group, and the determination result of the access determination unit.


Find Patent Forward Citations

Seki, Seiji. (2018). Memory control circuit (U.S. Patent No. 10108249). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10108249

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