The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Sep. 22, 2014
Applicant:

Panasonic Corporation, Osaka, JP;

Inventors:

Atsushi Yoshida, Osaka, JP;

Satoru Tokutsu, Saitama, JP;

Tomoki Ishii, Kyoto, JP;

Takao Yamaguchi, Osaka, JP;

Yuuki Soga, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); H04L 12/863 (2013.01); H04L 12/741 (2013.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
H04L 47/62 (2013.01); G06F 13/4059 (2013.01); H04L 45/74 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

In the bus system, bus interface apparatuses and routers are connected together through packet exchange buses which have been established on the integrated circuit. The bus interface apparatuses are respectively connected to transmission nodes which transmit data of mutually different numbers of bits in one cycle of operation of the bus system. Each of the bus interface apparatuses generates and transmits a packet based on data received from the transmission node connected and header information including size information indicating the number of bits with respect to the transmission node connected. The router analyzes the packet, gets the size information from the header information, determines how to allocate a space in the buffer for storage by reference to the size information gotten, and stores the received packet in the buffer.


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