The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Aug. 26, 2016
Applicant:

Infinera Corporation, Annapolis Junction, MD (US);

Inventors:

Vinod Narippatta, Bangalore, IN;

Mohammed Asad Rizvi, Bengaluru, IN;

Assignee:

Infinera Corporation, Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04Q 11/00 (2006.01); H04L 7/00 (2006.01); H04L 7/033 (2006.01); H04J 14/02 (2006.01); H04L 12/933 (2013.01);
U.S. Cl.
CPC ...
H04L 7/0075 (2013.01); H04J 14/021 (2013.01); H04L 7/0331 (2013.01); H04Q 11/0003 (2013.01); H04L 49/15 (2013.01);
Abstract

Systems, apparatus, and methods for packetized clocks may include a packet interface to carry the rate of a client to a sigma-delta modulator that generates a clock at the required rate inside the chip itself there by removing the need for off-chip analog PLLs. The packetized clock may include a packet interface that receives a flow credit packet that includes a plurality of flow credit counts, one flow credit count for each data flow, and forwards a flow credit count for each data flow to one of a plurality of clock generators to generate a new clock signal for each data flow.


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