The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Feb. 01, 2018
Applicants:

Jack R. Powell, Iii, Los Angeles, CA (US);

Alexander L. Braun, Baltimore, MD (US);

Inventors:

Jack R. Powell, III, Los Angeles, CA (US);

Alexander L. Braun, Baltimore, MD (US);

Assignee:

Northrop Gumman Systems Corporation, Falls Church, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/195 (2006.01); G06N 99/00 (2010.01); H03K 19/177 (2006.01); G11C 11/44 (2006.01); H01L 39/02 (2006.01); H03M 7/00 (2006.01); B82Y 10/00 (2011.01);
U.S. Cl.
CPC ...
H03K 19/195 (2013.01); B82Y 10/00 (2013.01); G06N 99/002 (2013.01); G11C 11/44 (2013.01); H01L 39/025 (2013.01); H03K 19/17708 (2013.01); H03K 19/1952 (2013.01); H03K 19/1954 (2013.01); H03M 7/003 (2013.01);
Abstract

An reciprocal quantum logic (RQL) gate circuit has a first stage having four logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and storing the SFQ pulses in respective storage loops each associated with a logical input, and a second stage having two more storage loops. First and second logical decision Josephson junctions (JJs) make determinations based on signals stored in the first-stage storage loops. A third logical decision JJ makes a third determination based on the first and second determinations. Each logical decision JJ triggers based on biasing provided by one or more currents stored in its associated storage loops and a bias signal having an AC component. The second stage asserts an output based on the triggering of the third logical decision JJ. Four-input AND, OR, AO22, and OA22 gates are thereby provided.


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