The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

Aug. 27, 2016
Applicant:

Samsung Electronics Co., Ltd., Gyeonggi-do, KR;

Inventors:

Yong-Hoon Son, Yongin-si, KR;

Jin-I Lee, Hwaseong-si, KR;

Kyunghyun Kim, Seoul, KR;

Byeongju Kim, Hwaseong-si, KR;

Phil Ouk Nam, Suwon-si, KR;

Kwangchul Park, Suwon-si, KR;

Yeon-Sil Sohn, Yongin-si, KR;

JongHeun Lim, Hwaseong-si, KR;

Wonbong Jung, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/41 (2006.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 29/408 (2013.01); H01L 29/4234 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01);
Abstract

A semiconductor memory device is disclosed. The device may include a stack including gate electrodes stacked on a substrate in a vertical direction and insulating patterns interposed between the gate electrodes, vertical channels passing through the stack and connected to the substrate, a tunnel insulating layer enclosing each of the vertical channels, charge storing patterns provided between the tunnel insulating layer and the gate electrodes and spaced apart from each other in the vertical direction, blocking insulating patterns provided between the charge storing patterns and the gate electrodes and spaced apart from each other in the vertical direction, and a bit line crossing the stack and connected to the vertical channels. The blocking insulating patterns may have a vertical thickness that is greater than that of the gate electrodes.


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