The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2018
Filed:
Aug. 24, 2016
Sfa Semicon Co., Ltd., Cheonan-si, Chungcheongnam-do, KR;
Hyun Hak Jung, Cheonan-si, KR;
Eun Dong Kim, Seoul, KR;
Jong Won Lee, Seoul, KR;
Jai Kyoung Choi, Busan, KR;
Byeong Ho Jeong, Hwaseong-si, KR;
SFA Semicon Co., Ltd., , KR;
Abstract
Provided is a method of manufacturing a fan-out type wafer level package. The method includes forming a fiducial mark pattern on a frame, attaching a semiconductor die to the frame with respect to the fiducial mark pattern, encapsulating the semiconductor die with a passivation layer, for reconstituting the semiconductor die as a wafer level, and sequentially forming a metal seed layer, a redistribution layer, an under bump metal (UBM) seed layer, an UBM layer, and a solder ball on a bonding pad of the semiconductor die upward exposed by an opening region of the passivation layer to finish a fan-out type wafer level package.