The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2018

Filed:

May. 24, 2016
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventors:

Takafumi Betsui, Tokyo, JP;

Nobuyuki Morikoshi, Tokyo, JP;

Tetsushi Hada, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); G06F 1/32 (2006.01); H01R 13/645 (2006.01); G06F 13/38 (2006.01); H01R 24/58 (2011.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); G06F 1/3243 (2013.01); G06F 1/3296 (2013.01); G06F 13/4282 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); G06F 13/385 (2013.01); H01L 2224/1623 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19105 (2013.01); H01R 13/6456 (2013.01); H01R 24/58 (2013.01);
Abstract

The semiconductor device has a semiconductor chip having a first-signal-output circuit operating at a first-power-supply voltage, a second-signal-output circuit operating at a second power supply voltage, and a plurality of bump electrodes; and a wiring board including a first main surface facing the main surface of the semiconductor chip, a second main surface opposite to the first main surface with a wiring layer therebetween, first external terminals on the first main surface, and second ones on the second main surface; the former being mounted on the latter to couple the bump electrodes to the first external terminals. When viewed from the second main surface, second external terminals to be supplied with the first signal and the second signal are arranged closer to the semiconductor chip than second external terminals to be supplied with the first power supply voltage and the second power supply voltage.


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