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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10103030 B1

PDFFull Text
Date of Patent:
Oct. 16, 2018

Filed:

Dec. 13, 2016

Methods of fabricating semiconductor devices

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Hyo-sun Min, Suwon-si, KR;

Yoonjae Kim, Seoul, KR;

Sooho Shin, Hwaseong-si, KR;

Sunghee Han, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Gyeonggi-do, KR;

Attorney:

Harness, Dickey, & Pierce, P.L.C.

Primary Examiner:

Timor Karimy

Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/306 (2006.01); H01L 21/265 (2006.01); H01L 21/283 (2006.01); H01L 21/308 (2006.01); H01L 21/768 (2006.01); H01L 21/822 (2006.01); H01L 21/033 (2006.01); H01L 21/3213 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 21/30604 (2013.01); H01L 21/0337 (2013.01); H01L 21/26506 (2013.01); H01L 21/283 (2013.01); H01L 21/3085 (2013.01); H01L 21/3086 (2013.01); H01L 21/32139 (2013.01); H01L 21/76895 (2013.01); H01L 21/8221 (2013.01); H01L 27/10823 (2013.01); H01L 27/10894 (2013.01);
Abstract

A method of fabricating a semiconductor device includes sequentially forming a first insulation pattern and an etch stop pattern on a peripheral circuit area of a substrate, forming a first mask pattern on a cell array area of the substrate, the first mask pattern including a pair of first portions extending in parallel and a second portion covering a portion of a sidewall of the etch stop pattern and a portion of a sidewall of the first insulation pattern, forming a second insulation layer covering the etch stop pattern and the first mask pattern, partially etching the etch stop pattern and the second insulation layer to expose the second portion of the first mask pattern, and removing the second portion of the first mask pattern to divide the pair of first portions of the first mask pattern.

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